Star Tech Journal

16
APRIL 1984
2
3
OUT
3
IN
78GUIC
OUT
2
s
IN
78GUIC
s
4
COM
4
FIGURE 1
The pinout of the 78GUIC looks
like (Figure 2):
1 =Common
2 = Input
3 = Output
4= Sense
4 3 2 1
1 2 3 4
joo o o
jooo o
Pao-Man
Ms. Pao-Man
Jr. Pao-Man
Silkscreen
Silkscreen
1 2 3 4
Front View
It is interesting to note this
power supply will still start regu-
lating with R53 out of circuit, so it is
not essential to setup.
It should be remembered that
the 6.2v zener (D9) is not actually
responsible for the determination
of the operating +5 volts. If so, then
the +5-volt supply would actually
be 6.2v. The 78GUIC determines
the +5 reference voltage. The way
in which it is used on the logic
board makes it work at its nominal
regulating voltage of +5v. It may, in
other applications, regulate from
+5vto 30v.
If one of these is bad on a board
you are troubleshooting and you
don't have another one, a 7805
three-terminal, +5-volt regulator
may be used. a 150Aresistor Is In
series with the ground terminal to
boost Its regulated output to 5.6v
to properly bias 050. Refer to
Figure 3 below for hookup.
FIGURE2
IR1 is mounted backwards in
the IR1 socket on the Pao-Man and
Ms. Pao-Man boards, so the wrong
schematic numbers seem correct.
But replace it according to the silk-
screen of the Pao-Man/Ms. Pao-
Man and it won't work. In fact, it may
burn up. The silkscreen on the Jr.
Pao-Man is correct as far as regu-
lator mounting, but this makes the
supplied schematic wrong.
CLOCK GENERATOR
The oscillator circuit consists of
the 18.432 Mhz crystal, R21, R22,
C4, and two gates of 1 0C.
The oscillator circuit is con-
nected to another buffer of 1 0C so
the oscillator works into a constant
load. This buffered 18.432MHz
clock is then fed to two flip flops to
divide the signal by three to approx-
imately 6MHz. The 6MHz and the
6M* signal are logical inverses of
each other displaced by 33¼ 0 • The
6M* is simply the logical inverse of
the 6M* signal.
These above clock signals are
reasonably clean square waves.
DIGITAL IN1, INE!, AND
DIPSWITCH
The logic designer used 74LS44
eight-buffer tri-state chips instead
of 74LS367 hex-buffers as was
used in Pao-Man. This reduced the
package count by one, since ittook
four 74LS367s to do what three
7 4LS244s do on Jr. Pac. Each chip
is uniquely addressed by chip 4C in
the address decode section. Note
1 OF and 1 OH chips are always being
probed so IN1 and IN2 are always
active. The dipswitches are
addressed only at reset so the 1 OE
chip is addressed by an active
DIPSW-enable only during test
mode and reset.
The resistor matrix for the inputs
of each chip (1 OE, 1 OF, and 1 OH)
are to insure logical highs instead
of floating inputs.
In particular, notice the AND
gate in the dipswitch section. This
gate is the final part of the 280 sync
bus controller section. It merely
allows two inputs WREQ and OPTN
lines to have control over the 280.
An active low WAIT-line (pin 6 of
4H) is a signal telling the MPU to
"wait its turn" to address the 6116
RAMs since the sync generator
also uses these RAMs to develop
the video picture.
SYNC GENERATOR
The horizontal count section com-
prised of 10D, 2R, and 2S are all
clocked simultaneously by the
6MHz line. These chips are cas-
caded to form a nine-bit binary
counter set to count from 128 10 to
511 10 and recycle. The vertical
section, comprised of 1 P, 1 R, and
1 S is driven by the HSYNC signal
from the sync generator section.
This nine-bit counter section counts
from 248 10 to 511 10. These hori-
zontal and vertical clocks are used
to address the video RAMs in an
orderly fashion. They are used to
clock the MPU (1 H), provide fre-
quency inputs to the sound section,
and to develop a stable video picture
by developing horizontal and verti-
cal timing and blanking pulses.
~ { Pin 1 of 7805 to Pin 2 of IR1 socket
~
Pin 2 of 7805 thru 150.0.. to convenient GND
Pin 3 to Pin 3 of IR1 socket
::,
...,
7805
7805
~
:!:
6
f
~
~3=0utput
2 = Ground
Front View
+5v Regulator
FIGURE3
{
Pin 1 7805 to Pin 3 of IR1 socket
Pin 2 7805 thru 150.n.. resistor to GND
Pin 3 7805 to Pin 2 of IR1 socket