Star Tech Journal

STAR*TECH
Journal
August 1996
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SEGA PINBALL WHITE STAR SYSTEM
CPU/SOUND BOARD THEORY OF OPERATION
TEAM SEGA
Joe Blackwell, Eric Winston, Ted Kilpin,Jay Alfer
Sega Pinball, Melrose Park, Illinois
CPU SEcnoN:
The CPU is a 68B09E (U209)
with up to 8Mbytes of CPU code
space in ROM(U210) . The CPU
code is bank selected by the use
of U211 and each bank consists
of 16Kbytes. 8Kbytes of
RAM(U212) is available to the
CPU. The RAM is battery
backed and has a write protected
area. Battery back up is accom-
plished by 3-AA Cells which
have a test point VBATT to
check the battery voltage status.
The write protected area consists
of 512 Bytes used for storing
game settings. This section of
RAM can only be written to
when the coin door is open. The
coin door switch comes into the
CPU on CN6-12 and is fed into
the address decoding PAL
(0213). When this memory pro-
tect signal is low writes to the pro-
tected RAM area are prohibited.
Address decoding for the system
is accomplished by one PAL
U213 and one 74LS138
1-of-8decoder(U214).
DEDICATED SWITCHES:
CN6 is a dedicated bank of in-
put switches. Switches connected
to CN 6 are connected to ground
instead of a strobe and may be
read at any time. The switch in-
puts are read through 0206 a
74HC245 Octal bus transceiver
with 3-state outputs.
Watchdog Circuit:
U218(DS1232)a watchdog is used
to monitor the CPU and the 5V
supply. If the 5V supply is below
4. 75 the watchdog will hold the
CPU board & I/O board in re-
set. The watchdog must be fed at
a rate of 25 Oms or faster. The sig-
nal used to feed the watchdog
comes from the EPRO M bank
select signal used to load 0211 a
74LS374 Octal D-type Flip-Flop/
Latch. The CPU has a timer in-
terrupt used as a heartbeat for the
system this signal comes from
counter U2. The clock for this
counter is the CPU Q clock.
Clearing the timer interrupt is
done by reading the DIP switch.
The timer interrupt can be ob-
served at test point FIRQ. In
normal operation "FIRQ''
should be toggling at a rate of
976Hz.
INTERFACE
TO
1/0
POWER
DRNER BoARD:
The I/O interface CNl is buff-
ered by two 74HC245 chips
0207 Data Bus & 0208 Address
and I/O Strobe. The CPU's re-
set line is buffered by QlO and
fed over to the 1/0 Power Driver
Bd. through CNL An 1/0 strobe
signal is fed through CN 1-15 and
is used to notify the I/O that a
valid address is being sent.
TEST POINTS:
E & Q - The CPU signals for
both 68B09E processors. Should
be at 2Mhz with Qleading Eby
500 nsec.
24Mhz - The oscillator used for
the BSMT & derivation of E &
Q
FIRQ-The
games CPU
interrupt.
SND-FIRQ
- The sound
sections
CPU inter-
rupt.
6Mhz-This
clock is gen-
erated internally on the BSMT
and is used for shifting the data
samples into the DAC.
AOL & AOR- Audio output left
and right.
5 Volts & GND - Used for check-
ing 5 volts on the CPU Bd.
Reset(s) These are active low sig-
nals and under normal operation
should be high. The Reset(Test
point)is electrically connected to
sw200, this switch forces a reset
from the watchdog IC. U218.
The SND-Reset is a latched sig-
nal that controls when the sound
microprocessor begins to run.
VBATT - Used for checking the
voltage output of the battery pack
when the power is turned off.
Please see schematics on page 19 & 20.