Star Tech Journal

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The serial Frame Number(FDATA)
is then shifted into three serial-to-
parallel shift registers, B1, G1, and
H1, by the FCLK signal. Within the
Frame code we have to represent
numbers from 1 to 54000, one for
each video frame. One binary coded
digit (BCD) can be represented by
four binary bits, so the five digits of
number 54000 will be represented
by 20 bits. The high order four bits
of the 24-bit Frame Number code
are all ones, which will be shifted
rnto the high orders four bits of the
most significant shift register (B1)
and generate the Valid Frame
Number latching pulse. The dual
four-input NANO gate (E1) is con-
figured to detect the four high bits
and generate a clocking pulse that
latches the Frame Number into the
8-bit latches B2, G2, and H2. The
game machine CPU will strobe the
input port functions IP5, IPS, and
I P7 to read the Frame Number onto
the data bus.
AUDIDTRACK
DECODER
The video disc has not only com-
posite video information stored on
the disc, but also contains two
separate discrete audio channels.
One channel contains pure sound,
such as the jet noise and voice,
which is routed directly to the AS
Sound Board for pre-amplification.
The other channel contains a
digitally encoded audio frequency,
which carries target information
relating to the game play and proper
placement of targets, and the
horizon.
During active play time of the disc,
the Audio Track 2/R will be contin-
uously transferring serial digital
data to the Audio Track Decoder
section at a 5-KHz rate. Approxi-
mately every one and a half seconds
the Interface Board will have re-
ceived a 1 K block of digital
information which will then be
transferred to the game machine
CPU.
The digital data coming from the
audio track is encoded in an audio
frequency, rising and falling across
the zero volt level at its own clock
rate. The audio track must be
decoded to determine the clock
rate and to detect transitions through
ground to generate positive pulses.
The Audio Track 2/R is a 1-volt
peak-to-peak signal which comes
into JS. The audio signal is first sent
to an amplifier(R46, R47, R48 and
03) through C78 to give a better
signal-to-noise ratio. The 5-volt
peak-to-peak signal passes through
a DC clamping circuit (C79, D 1, and
D2), a biasing network (R10 and
R11 ), a low pass filter (R36 and
C10), and on to the zero crossing
detector (X4). The IC X4 is a dual
voltage comparator that has been
configured to be a zero crossing
detector. Both outputs of the zero
crossing detector are tied to a two
input AND gate (S4) which will
produce a pulse train at pin 8 that is
high when the input wave passes
through a 1 00mV window around
ground. This signal is sent to E3,
M5, and V5, so that the data clock
and break in transmission signals
can be formed.
the output is also connected to a
data detector consisting of A4 and
S2. Th is circuit determines whether
an edge is detected between clock
pulses, indicating that a logic "1"
was received at the zero crossing
detector. When that occurs, the
data detector generates a high
pulse to be clocked into a serial to
parallel converter(K1) via the clock
from the clock generator (M5).
As the parallel data is received it is
sent to a bus transceiver (M1) and
to a Buffer Starts Detector, (N3 and
N2) which will detect the buffer
sync byte, 67, the first byte in the
1 K block of data. A high pulse is
produced at N2, pin 2, when the
buffer sync byte is detected. This
high pulse is inverted by the NANO
gate (S3) and clears the Buffer
Ready Flag D flip flop (V4) and the
RAM address counters (V1, V2, and
V3) through the AND gate (S4). The
audio track data clock will begin
clocking the Module 8 Counter(V4
and N4) which will generate the
RC LOCK function every eight data
bits. The RC LOCK function is multi-
plexed through the RCLOCK MUX
(S3) to generate the clocking pulses
for the RAM address counters. The
RAM address counters then
sequentially address the Buffer
RAM (S1) to store the 1 K block of
data from the audio track for the
game machine's later use.
The CPU machine, as mentioned
earlier, has several input and output
port select lines connected to the
Interface Board to control certain
portions of the board. To access
the Audio Track Decoder section
the game machine CPU will use the
OPS and OP7 functions in conjunc-
tion with the DO bit to create two
latching functions, STB1 and STB2,
(B3 and E3). The function STB1 is
used to read the Status Register
(E2) to report to the CPU the condi-
tion of certain portions of the
interface circuitry.
One of the status functions read by
the game machine is the Buffer
Ready Flag (V4), which is pulled
high when the most significant bit
of the RAM address counters goes
high. This indicates that the Buffer
RAM (S1) has been filled with the
1 Kblockofdata The game machine
then pulls the DO bit low as it strooes
the OPS function fort he B3 flipflop
to change output states. The Q
output of B3 is OR'd with I P7 strobe
to produce STB2.
The RCLOCK MUX circuitry is made
of 3 two-input NANO gates con-
figured so that if the Buffer Ready
Flag is low, then the RC LOCK func-
tion will be used to determine the
clocking rate for the RAM address
counters. When the Buffer Ready
Flag goes high, it enables the game
machine to set the clocking rate
with the STB2 function through the
RCLOCK MUX. The STB2 signal is
sent to a Schmitt trigger inverter
(A2), and to a monostable multi-
vibrator (B4) for glitch-free pulse
shaping of the signal to match the
data transfer rate of the game
machine CPU. This pulse shaped
signal (MSTB2) will now sequentially
increment the RAM address
counters, while the STB2 function
will read the data on to the Data
Bus through the eight-bit buffer
(K2).
COMMAND
CONTROLLER
The Command Controller section of
the A2 Interface Board creates the
means by which the game machine
sends instructions to the video disc
player. The video disc player has
26 functions, such as freeze frame,
fast forward, search to frame, play,
reverse, etc., that can be controlled
from an infra-red generating remote
control unit, or from an External
Control input port at the rear of the
player. The External Control port is
a serial, two-wire, interface input
that disables the remote control
receiver when connected.
The Command Controller section,
therefore, is a serial interface
encoder and transmitter. It not only
converts
the
parallel,
8-bit
command from the game machine
CPU to a serial format, but must
also generate the protocol neces-
sary for the control section to
communicate with the video disc
player. The correct protocol con-
sists of a series of bursts of a carrier
frequency, with the bursts separated
by a specific length of time that
determines whether a "0" ora"1" is
being transmitted.
Any of the 26 commands can be
encoded using a serial 11-bit pulse
code modulation (PCM) scheme.
The PCM scheme means to modu-
late the time between the bursts to
indicate the "0" or"1" status of the
bit within the code. Each pulse
burst consists of 10 pulses of the
38 KHz carrier frequency and is
approximately 0.263 milliseconds
long. The elapse time between
bursts, termed the Bit Period, is
either 1.05 milliseconds to indicate
a logic "0" or 2.1 0 milliseconds to
indicate a logic "1".
ThegamemachineCPUwillinitiate
a command transfer through an-
other output port function, OP7.
The OP7 function latches the CPU's
command from the data bus into a
parallel-to-serial shift register (M2)
23
and also resets the Start Transmis-
sion Flag (W2). The Start Transmis-
sion Flag enables the counter chain
made up of X2, W1, and X1 and the
burstclock(X3) a LM555 timer. The
LM555 timer produces a 38 KHz
clock signal to the counter chain
when pin4 is high. The clock can be
calibrated with the Self-Test mode
or by moving jumper JP14 from
normal to test and adjusting R22
until the period of the signal at pin 3
is 26 usec.
One half of W2, a D-type flip flop,
generates the Start Transmission
Flag while the other half is used to
gate the38 KHz bursts to the output.
A presettable decade counter (X2)
is used as a Burst Counter which
strobes W2 to gate 1 0 clock cycles
to the output. W1 is a data-to-period
counter which receives the serial
data output from the parallel-to-
serial shift register(M2). If the data
from M2 pin 9 is a logical high, the
W1 is preset with an 8 which pro-
duces an approximately 2.1 msec
period. If the data is a logical low,
the W1 is preset with a binary4 that
produces an approximately 1.05
msec output period. The IC X1 is a
Bit Counter which counts 11 bits
and then disables the Start Trans-
mission flip flop and sets the End of
Transmission Flag. When the End
of Transmission Flag is high, the
game machine CPU will read it
through the Status Register (E2) to
allow the CPU to send another
command if it needs to.
CONCLUSION
The proper operation of the game
system is the normal condition
under which these circuit descrip-
tions apply. Of course, a defective
Interface Board will halt proper
game operation, possibly even
prevent initialization. The use of
the Self-Test mode in the game will
aid the technician in troubleshooting.
When entering any specific test in
the Video Test section of the Self-
Test mode, the game machine CPU
will begin to send commands to the
Command Controller section and
look for responses from the Status
Register. This will allow a technician
to check the Command Controller
section. Until a specific test is begun,
thegamemachinewillstayinawait
state, so by pressing the "Play"
button on the front panel of the
video disc player, the disc will spin
up and output its signals to the
Interface and Color/Sync Boards.
A technician can now check the
input and initial decoding of the
Frame Number and Audio Track
Decoder sections.