Star Tech Journal

S• TJ NOVEMBER 1981 13
INTERFACING DYNAMIC 4027 RAMS TO THE Z80
Sixteen-pin dynamic
RAM's are increasingly
being used as the memory
component for data
storage in microprocessor-
based systems. Their
popularity over static and
18 or 22-pin dynamic
RAM' s has been the result
of a maturing memory
technology and the char-
acteristics of the devices
themselves. Their main
features are low cost/bit
and high bit density; addi-
tional features include a
low standby power mode,
TTL-compatible inputs
and outputs and system-
upgrading expansion capa-
bility. Replacing the chip-
select pin on the 4K device
with an additional address
line effectively quadruples
memory capacity to 16K
bits. It is now possible,
for example, to assemble a
full 65K-byte memory sys-
tem on a single printed-
circuit board in an area of
less than 50 sq. in ..
Now however, the system
. designer must be con-
cerned with the interface
requirements of 16-pin
dynamic RAMs. The char-
acteristics of this memory
element require that re-
freshing of the memory be
performed at periodic
intervals in order to retain
the stored data. This,
coupled with the require-
ment for multiplexing
address lines, has been the
main drawback to their
use. A typical interface
requires approximately 12
to 20 standard TTL
devices and includes
timing generators, decode
logic, multiplexer circuitry,
refresh logic and buffers.
The Zilog Z80A micro-
processor is designed to
simplify this interface with
built-in refresh logic,
which allows totally trans-
parent RAM refresh with-
out the need for a refresh
counter or it's associated
multiplexer.
16-PIN DYNAMIC
RAM ADDRESSING
Each cell of a dynamic
RAM array is arranged in
a matrix. Selection of a
unique bit location within
this matrix in a 4K RAM
requires 12 address lines,
while a 16K RAM requires
14. For a 16-pin RAM to
accommodate these lines,
it must divide them into
PIN CONFIGURATION
4027
-5
D-IN
WE
GRND
CAS
D-OUT
RAS
cs
A2
A,
A3
A.
As
Ao
+12
+5
two groups-row addresses
and. column addresses (six
each for the 4K RAM and
seven each for the 16K
RAM).
Each group is applied to
the RAM on the same in-
put lines through an
external multiplexer and is
latched into the chip by
applying two clock strobes
in succession. The first
clock, the row-address
strobe (RAS), latches the
row address bits (A-0 to
A-5 for 4K, A-0 to A-6 for
16K) into the RAM. The
second clock, the column
address bits (A-6 to A-11
for 4K, A-7 to A-11 for
16K) into the RAM.
Each cell therefore is
uniquely addressed by row
and column. When RAS
goes active, all of the
cells in the selected row
respond (there are 64 rows
in the 4K RAM matrix
and 128 rows in the 16K
RAM matrix) and are
gated to sense amplifiers
where the logic level of
each cell is discriminated,
latched and rewritten.
CAS activates a column in
the matrix (there are 64
columns in the 4K RAM
matrix and 128 columns in
the 16K RAM matrix)
that uniquely identifies
the cell in the row output
and yields the required bit
to the output buff er.