Play Meter

quantities , ingredient additive rates,
and process steps are carefully
followed to insure maximum yield of
the finished parts.
One wafer may easily produce
1500 to 2000 individual silicon chips.
Circuit dice are typically .025 inch
square to .025 by .045 inch. The
number of legs the I. C. will have,
determines the geometry of the
circuit dice ,
As the wafer fab process continues
it sequentially increases in complexity
and therefore the quality assurance
becomes as important as the resolu -
tion of registration.
The thin sliced wafers move from
the clean-and-polish area into the
photolithography section which is
typically under yellow light. Here the
process begins by shooting a minute
pattern ( image) onto a photochemi-
cally treated wafer.
In fact , there are many steps
included in this series before the
wafer moves into another area .
Basically , the wafer has an image
deposited all over it with a film
master or a step and repeat camera,
depending on the process require-
ments.
Then the area which is exposed
through the image is etched away in
a negative resist process and remains
in a positive resist process. General-
ly , the lesser amount of material is
etched away . Therefore, the film
masks reflect the negative process .
Quite simply, the wafers are coated
with a developer which makes it react
like a film negative.
Then the wafers are dipped in an
acid etchant bath for a period of time
which determines how much of the
raw silicon will be etched away. Nitric
acid is the commonly used etchant
and has a reaction value which is
determined by the concentration of
the acid .
At the end of the etch process you
have a wafer with tiny holes and
patterns etched into it. The typical
depth of the etched area is 1500 A to
2500 A units-just enough area to
make a difference in the flow of
electrons through the surface layers.
There are so incredibly many
variables in process considerations
that it is overwhelming - so I'll move
on to the next phase of the process .
Now we have the exposed
windows in the silicon surface , so we
must fill them with something. These
are our choices of process steps :
epitaxial reactor, diffusion furnace ,
vacuum evaporator, E-beam evap-
orator , R-F sputtering and some
electrochemical processes. All these
names are references to the types of
equipment which produce relatively
the same effect: a method to deposit
another semiconductor material into
the holes, windows , and patterns
which the etching process left.
The major difference is the size
that all things have been reduced to .
The circuit traces are frequently one
half a thousandth wide. The metali-
zation area for lead attack is two to
five thousandths square , and the
depths of the junctions which have
been created in the evaporation
process are less than 5000 A at best.
Everything has been reduced
down to the sub-atomic level where-
by the addition of too many atoms
during depositation is enough to vary
the thickness of the junction and alter
the
performance
of
the
part
significantly .
The combinations of photolitho -
graphic , chemical , and deposition
processes continue until the part is
completed . In other words, the
recipe is complete when it includes all
the oven work .
Generally , the last step in the
wafer fab process is the controlled
addition of oxides , called passifica -
tion . It is amazing that we ended at
the same place we started. First , we
guarantee there are no 02 combina-
tions; then at the end , we add them .
The answer is simple: when 02 is
added correctly it reacts with other
host materials and becomes a form of
glass . Therefore , when you have
completed the wafer fab process , you
seal the part, with its delicate and tiny
pattern, under glass. A very thin
layer of glass such as Si02 - also
known as silicon dioxide window
glass.
The chip
When the wafer fabrication pro-
cess has been completed, the wafer
consists of a thousand or more
processed images arranged in an
X -Y coordinate system with narrow
spacing between the rows and
columns .
The next step in the overall
scheme is the die testing which is
performed
by
automatic
wafer
probers . Typically , the big Fairchild
and Teledyne systems , which are
specifically designed to emulate the
chip under load , will test all die
elements and ink out any chips which
fail the test.
When this is done , some minutes
after you start , you have a processed
wafer capable of being handled with
finger cots and moved into the next
process area , wafer scribe . At this
point , the inked wafers are placed in
wafer carriers for more convenient
handling .
Previous to this time, the wafers
were placed in boats , wafer carriers ,
and / or planatary assembli es during
handling and processing . But now ,
th e wafers are not in need of such
criti cal and stringent handling pro-
ce dures.
Th e w afer saw or wafer scribe
operati o n is an absolute abuse
co mpared to wh at th e delicate wafers
have bee n previously expo sed to.
Th e wafer sa w is a di am o nd dust
carbo rundum blade. abo ut .00 3 in ch
thick at th e tip . less than three in ches
in diam eter . and spin s at 10 ,000
RPM .
Th e m achin e is generally pro-
gramm abl e fo r its X ( verti cal) , Y
( hori zo ntal) . and 0 ( th eta) travel.
Th e ta is th e arch which is d erived
fro m w arp age of th e wafer during
processing .
Th e w afer saw cuts th e dice row by
ro w and co lumn by column . This is
accomplished o n a vacuum chuck so
as to ho ld th e w o rk in pl ace. Or . th e
wafer is cut o n a thin adh esive pad
which acco mplishes th e sam e result.
After this. th e tin y dice are o ff -loaded
int o th eir carriers and p ackaged with
a mo isture absorbing m aterial until
th ey are read y for asse mbly .
In co ntrast. the wafer scribe
operation is just as it suggests . The
die elements are scribed between
each row and column , and scribed so
th at th e depth of th e cut is at least 1 12
to % th e to tal thickn ess of th e wafer.
After all ro w s an d columns are
scribed . th e wafer is rem o ved from
th e va cuum chu ck. placed o n a tru e
and flat machin ed surface and rolled
ove r with a small rolling pin .
All th e di e elem ents just fracture at
th eir p erim eters and la y th ere until
th e operator picks them up with a
vac uum pencil. Again. th ey are
placed into littl e hold ers until th e
asse mbl y o peration is turn ed on .
A s an int eresting no te, yo u would
think that with so m an y dice coming
fro m o ne wafer , and so man y wafer
fro m o ne ingot . th ere w o uld be a
surplus of int egrated circuits . The
truth is. th ere is reall y only o ne third
o f th e pro du ct th at is mad e that is
ava ilabl e at an y on e tim e. Th e se mi -
co ndu cto r m anufacturers have estab-
lished an assembly procedure where-
by they send their processed wafers
to the Orient for assembly. There-
fore , you have a quantity of wafers in
process here in Silicon Valley, a
qu antity of wafers in test and transit ,
and a quantit y of wafers being
packaged and in tran sit throughout
th e distributi o n chain .
Wh y th e Oriental o p erati o n?
Purely a cost sav ings.
L oo k at a se miconducto r chip and
read what country it was assembled
in . I'll bet it w as mad e in Mal aysia.
M exico. H o ng Kong. Taiwan . or
K orea .
Wh at ever happened to Am eri can
tec hn o logy? It is in side th e package .
covered up .
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