10
STAR*TECH JOURNAL/MAY 1983
SEGA ELECTRONICS'
ROM LINE (PART 8)
PRICE
CONVERSION
BREAKTHROUGH!
FOR ROWE
CIGARETTE
'MACHINES
In this issue we will continue our review of TTL
circuits.
7404 HEX INVERTER:
Figure l illustrates an integrated circuit containing
six simple inverter circuits. Each circuit functions
simply to invert the state of the voltage applied to
its input. If the input is LOW, the output will be
HIGH. Conversely, if the input changes to a
HIGH state, the output will immediately change
to a LOW state. Thus, it "inverts" the signal
applied to the input terminal. Inverters are used
primarily to invert a signal that is of the wrong
polarity to interface with, or drive, another circuit
or device.
7404 HEX INVERTER
FIGURE 1
• Will vend up to $1 .75 in
increments of 5¢.
• Same mechanical
dependability using your
present totalizer. No
electronic components.
• Accepts any combination of
nickels, dimes and quarters.
• 4-minute installation on
location OR
• Send us your totalizer - we
will convert it ($5.00 service
charge).
PRICE
REDUCED
7408 AND GATE:
Figure 2 depicts a Quadruple 2-input AND gate,
the 7 408. In operation, the output of each gate will
go HIGH only ifboth inputs are HIGH. Restated,
the output will change to a HIGH state only when
both input l AND input 2 are HIGH. It is therefore
called an AND gate.
Consider a typical application: If input l
remains at a LOW state, the output will be LOW
and any changes at the other input will not affect
the output. However, if input l then goes HIGH, it
will allow the changes at the other input to appear
at the output. Returning input l to the LOW state
will again cause the output to go to the LOW state
and inhibit any further signals at input 2 from being
felt at the output. Thus, the signal at input 2 has
been "gated" to the output by a signal applied at
input 1. Hence the term GATE.
7408 QUAD 2-INPUT AND GATE
$29.95 (In Lots of 10)
1 to 9 Units - $34.95 each
Input information is applied at the "D" input.
This may be either a HIGH or LOW potential.
The input is transferred to the Q output upon the
positive transition of a pulse applied to the clock
(CK) input. For instance, if a HIGH is applied to
the " D" input, and held there, no change in the Q
output will be noted until a clock pulse is applied to
the CK input. When the positive edge of the clock
pulse occurs, the HIGH felt at the input will be
transferred to the Q output. Any additional clock
pulses that occur while the " D" input remains
HIGH will cause no further change. However,
should the " D" input go to a LOW state, the
positive transition of the next clock pulse will
cause the Q output to go LOW.
_ The "D" Flip-Flop also has a Q (pronounced
"Q-Bar'') output, which simply provides an output
that is always the opposite of the Q output. IfQ is
HIGH, Q will always be LOW, and vice-versa.
Input information is applied at the "D" input.
This may be either a HJGH or LOW potential.
The input is transferred to the Q output upon the
positive transition of a pulse applied to the clock
(CK) input. For instance, if a HIGH is applied to
the "D" input and held there, no change in the Q
output will be noted until a clock pulse is applied to
the CK input. When the positive edge of the clock
pulse occurs, the HIGH felt at the input will be
transferred to the Q output. Any additional clock
pulses that occur while the "D" input remains
HIGH will cause no further change. However,
should the "D" input go to a LOW state, the
positive transition of the next clock pulse will
cause the Q output to go LOW.
A "D" Flip-Flop also has two other inputs
labeled "PRESET" and "CLEAR". These inputs
may be used to set the outputs to a desired state.
With both the PRESET and CLEAR inputs held
HIGH, the circuit will operate normally. If a
LOW is applied to the PRESET input, it will
cause the Q output to go HIGH. Conversely, if a
LOW is applied to the CLEAR input, it will cause
the Q output to go LOW. It is important to note
that a LOW input to either the PRESET or
CLEAR will override any other input functions.
It should also be noted that clock triggering
occurs on the positive-going transition of the clock
pulse; thus, the 7474 is called an " edge-triggering"
Flip-Flop. Triggering occurs at a voltage level of
the clock pulse and is not directly related to the
transition time of the positive-going pulse. After
the clock input threshold voltage has been passed,
the data input "D" is locked out, and any change in
the "D" input after that time will not affect the
outputs until the next positive-going transition of
the clock pulse.
7474 DUAL D-TYPE EDGE-TRIGGERED
FLIP.FLOP
All orders shipped UPS/COD.
TELEPHONE:
516-928-6868
COIN UP-DATE
INDUSTRIES, INC.
14 Hulse Road
E. Setauket, NY 11733
FIGURE 2
7474 "D" FLIP.FLOP:
The circuit shown in Figure 3 is a Dual D-Type,
Edge-Triggered Flip-Flop. It is a relatively complex
circuit made up of several of the gates discussed
above. It is conventionally shown as a "block"
diagram with input and output functions designated
as shown, and it operates as follows:
FIGURE 3