STAR*TECH JOURNAL/JUNE 1983
5
tMNUFACTsO
INTRODUCTION TO THE 68000
By Don Becker, Atari Inc., Somerset, NJ
Two of Atari's latest games, Quantum and Food
Fight, are using the new 68000 microprocessor.
Since this will be the first time many of you are
exposed to a 16-bit machine, I thought that this
month we would take a look at what it takes to run
a 16-bit processor - specifically the 68000.
When they call the 68000 a 16-bitprocessor,
they are referring to the number of data lines.
Older microprocessors utilized an 8-bit data bus
and a 16-bit address bus, as opposed to the
68000's 16-bit data bus and 24-bit address bus.
This added capacity means that the 68000 can
process twice the information that an 8-bit
machine can in the same amount of time ( assuming
both processors run at the same clock speed). The
24-bit address bus gives us the ability to directly
address up to 16 megabytes of memory.
To control this type of capacity, the 68000
uses some special signals not ordinarily found on
an 8-bit machine. We will start with the bus
control lines and the first of these we will talk
about is AS, the Address Strobe. This signal is an
output from the processor and indicates that there
is a valid address on the address bus. The second
signal, R/W, should be familiar to all as the
standard Read/Write signal. The next two signals
are unique to 16-bit machines and thus deserve a
little more attention. These signals are UDS and
LDS and they stand for Upper Data Strobe and
Lower Data Strobe. These two signals allow the
68000 to split its 16-bit data bus into two 8-bit
data buses.
UDS controls data bits 8--15, and LDS controls
0-7. All this means is that UDS will tell a device
connected to the 68000 that the data it sees on
D8-D15 is valid and LDS will tell it that what it
sees on DO-D7 is valid.
So far, all of the signals we have talked about
have been outputs from the processor, but there is
one bus control line that is an input and this is
DTACK. DTACK, or Data Transfer Acknow-
ledge, is a signal from another device telling the
processor that the data it put on the bus has been
received. This is an example of"handshaking", a
process the 68000 makes extensive use of. Every
time the processor transmits or receives data on
the bus, it requires a DTACK before it will
transmit or receive the next word ( 16 bits). If it
does not receive DTACK, it will just sit there all
day waiting until it does.
The next group of signals are the processor
status signals, or function codes. These three
outputs FC0, FCl, and FC2 indicate the state
(user or supervisor) and the cycle type ( data,
program, or interrupt acknowledge) currently
being executed. These signals are valid whenever
AS is active.
After these we come to the bus arbitration
control. These signals BR, BG and BG ACK are
simply to determine who has control of the bus at
any time, be it the processor or an external
device.
BR, or Bus Request, is an input to the
processor from another device and tells the
processor that someone else would like control of
the bus.
BG, or Bus Grant, is an output from the
processor telling the other devices that at the end
of the current bus cycle, the processor will release
control of the bus to another device.
The last of these signals is BG ACK, or Bus
Grant Acknowledge. This is an input to the
processor telling it that the other device has taken
control of the bus. A device having control of the
bus is said to have bus mastership. Putting them
all together then, we see that an outside device
~ch as a DMA controller) asks for control on
BR, the processor grants its request on BG (you
may have control), and the device replies back on
BGACK (Thanks!).
~ x t we have the three system control Jines,
BERR, HALT, and RESET. The RESET line
on the 68000 is a little different than we are
ordinarily used to, in that it is bidirectional. This
means that not only can we reset the processor by
pulling RESET and HALT low, but the processor
can reset other devices on this line by executing a
reset instruction. When this happens, all devices
connected to the RESET line are reset, but the
internal state of the processor remains unaffected.
When the processor is reset externally, all of the
devices on the reset line are also reset and the
processor begins executing instructions from
address 000000.
BERR stands for Bus Error, and this signal
tells the processor that there is a problem with the
cycle currently being executed.
The 68000' s HALT line is also bidirectional,
and when driven by an outside source, it causes
the processor to stop at the completion of its
current bus cycle. When this occurs, all control
signals are inactive and all three state lines are put
in their high-impedance state.
The next set of control lines we come to are
the interrupt control lines IPLO, IPLI, and IPL2.
These three Jines indicate the priority of the
device requesting an interrupt Level seven is the
highest priority, while level zero indicates that no
interrupts are being requested.
Last we have the M6800 peripheral control
lines E, VMA, and VP A. These three lines allow
the 68000 processor to interface with 6800
peripheral devices ( the 6800 is an 8-bit device). E
is the enable signal, standard to all 6800 devices.
VMA, or Valid Memory Address, tells the
peripheral that there is a valid address on the
address bus.
VPA stands for Valid Peripheral Address,
and this just indicates that the device addressed is
a 6800 device.
The 68000 is one of the first 16-bit processors
to be introduced to the video game industry, and
because of their speed and data handling capability
you will undoubtedly see more of them in the
future. Becoming familiar with them now will
save you many service headaches later on.
PIN ASSIGNMENT
D1
DO
LDS
DTACK
BG
BGACK
BR
vcc12,
CLK
GND
GND :2I
CLK
HAIT
RESET
VMA
Processor{
Status
FCO
FCl
FC2
E
M6800 {
Periphera
Control
VMA
VPA
0
E
ii
BEAR
::;; e
0
~
rum
System{ ~
Control
HAL'f
Input and Output Signals
Al