Star Tech Journal

Issue: 1983-June - Vol 5 Issue 4

17
STAR*TECH JOURNAL/JUNE 1983
DISPLAY CONTROL DIAGRAM
&~tk
1 K X 3
tape deck will pause again. During the tape
deck pause, the data is being verified. If the
data is correct, the data counter will decrement
by one, and the next block of data will be read
This will continue until the data counter reaches
001. At 001 the CPU will issue a rewind
command to the tape controller, and the cassette
deck will begin to rewind the cassette tape. The
tape will rewind for about 1 minute. The tape
will stop rewinding when the clear leader
portion of the tape is sensed. After the loading
process has taken place, the CPU then begins
to initiate the game program. The game is now
ready for play. The cassette loading process
will take place daily upon power up.
Beginning of Tape
THEORY OF OPERATION
When power is initially turned on, the system
CPU clears the display RAM and prints Deco
Cassette System. At this point, the CPU issues
a rewind command to the tape controller. The
tape will rewind and stop at the clear leader
portion of the cassette tape. The tape deck has
a light sensor circuit (see photos at right). It
consists of a photo sensor and a light-emitting
diode. When light from the LED passes through
the clear leader of the tape, the photo sensor
will detect it, and send a signal to the tape
controller CPU. The tape will then advance
until it reaches the beginning of tape (B.O.T.).
The tape deck will then pause. The B.O.T. is a
small hole in the cassette tape. The tape will
advance, and data will begin to be transferred
to the dynamic RAM. A counter will be
displayed on the system monitor. The number
count represents the number of256--byte blocks.
Data is read into the cassette interface. The
Keepvourg
ameson
Clear Leader
TAPE DECK
PHOTO SENSOR
LED
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Next month, the installation procedure for
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published
18
STAR*TECH JOURNAL/JUNE 1983
* PAO SHOW* R·S LATCH OPERATION * KEYBOARD PROGRAMMABLE DIVIDE-BY-N COUNTER
* SCOUTBALL TROUBLESHOOTING TIPS FOR LIGHT OR SOUND FAILURE
By Mark "Bear" Attebery, Vending International Corp., San Juan Capistrano, CA
Well, first of all, I did not attend the Pacific Operators Expo at the Disneyland
Hotel in Anaheim, California ( only 30 miles away!). But, since I was in Japan, it
tended to be too long a trip! From the sales people who attended and worked
Vending Intemational's booth for the show, it seemed as if the show was a
moderate success (which is saying alot for a brand new show) and was
organized well for the number of exhibitors who were there. The only problem
evident was low attendance, possibly caused by the price of admission being
$25 .00, and maybe not enough direct promotion such as flyers, letters, etc. But
the idea of a West Coast show was well accepted! Like I said before ... the low
attendance was the only problem!
Now on to more cheerful notes ... Future Tech Lesson #4!
Since we've got the Basic S.S.I. circuitry down, let's look at what some
people call M.S.I. (Medium or Middle Scale Integration). M.S.I. is not a
commonly used acronym. Most technicians stick with S.S.I. or L. S.I. and, since
• I also follow this procedure, you'll see why we call an R-S latch S.S.I. Even
though, to look at the chip's integrated circuit component breakdown, it looks
quite complicated, the R-S latch is easy to understand and use. Using a 4044
quad R-S latch (CMOS) as an example, an easy way to picture an R-S latch is
as a single relay SW with magnets on both sides. Such as ...
r - ---
T ~
=l
- - - o : -=- ) 0 (OUl)
s
1
~
I ____ _!-=-
using this to operate your truth table, you will see the following ...
R r---7
vcc
0
'
o I=-
S1
0
'
~
I
I
=
)O(OUl)
When both inputs are "0", the
output is "0".
) 0 (OUl)
When R is"1" and S is"0", then
the output is "1 ".
~
"The CD4044BM/CD4044BC IC contain four cross-coupled TRI-STATE
CMOS NAND Latches. Each latch has a separate Q output and individual set
and reset inputs. There is a common TRI-STA TE ENABLE input for all four
latches. A logic 'I' on the ENABLE input connects the latch states to the Q
outputs. A logic '0' on the ENABLE input, disconnects the latch states from the
Q outputs resulting in an open circuit condition on the Q outputs. The TRI-
ST A TE feature allows common bus sing of the outputs."
(TRI-STATE) is a trademark of National Semiconductor Corp.)
OK, with the given inputs, tell me what the outputs will be ...
A·O
B-0
D-1,R
02
E-O~O
F-1 o - - - - - - - '
G·O 0 - - - - - - - - - - . . . . ,
Look for the answers at the end of the article.
OK! I promised a keyboard programmable divide-by-N counter that when
hooked to the pulse generator as described in last month's StarlrTech Journal
column, would produce a decent programmable frequency clock source for
digital experiments or board repair. So here we go! You'll be using two 74C74
(or 7474 if you're using straight TTL) IC chips, one 74C86 (or 7486 if you're
using straight TTL) IC chip, one 74C922 (or 74922 as before!) and sixteen
single pole, single throw push button switches, four 4 7k ¼ watt resistors, one I uf
polarized tantalum capacitor, and one 0.1 uf capacitor.
Your 74C74 IC chips are Dual D Flip-Flops. Your 74C86 is a package of
four two-input Exclusive OR gates, and the 7 4C922 is a 16-key encoder. (There
are other encoders on the market that can also be used, i.e., Radio Shack,
E. C. G., and others that will have similar mechanics but possibly using different
pins.) Here is your schematic:
R ,- - - - 1
vcc
t
KEYBOARD PROGRAMMABLE DIVIDE·BY·N COUNTER
~
1
I 0---Q: I -
='
~
51
0
1----J
l-74C86--I
f·in,..,p,....u_t _ _ _ _ _ _ _ _ I_1-'II
";C""
12
74C922
VCC
t
0
vcc
>O (OUl)
When Sis "1" and R is "0", then
the output is "0".
>0(0Ul)
but if both pins are "high", then
the switch has an equal amount
of pull from both sides. If it's
already closed, it will remain
closed. If it's alreay open, it will
remain open.
R 1---7
~
t1
1--1-
'------,1--~,
8 1=1
~
E
a
X
X
0
Tri-State
(High Impedance)
0
0
1
1
0
1
0
1
1
1
1
1
0
1
0
No chang·e
!
:~----;i
.-+--------10
CLK
I
74
SPST Push
Button Switches
4044 R·S Latch Truth Table
R
I
I~--
Now, this is just a very simple example of how the R-S latch works and we
haven't included the ENABLE pin into our discussion yet, because I can't
figure out a way to illustrate its function. So, I'll give you the 4044's truth table
and quote its "General Description" out of a CMOS Data Book.
s
I
3
')------------,
X = DON'T CARE
1 uf
f,;
I
74
I
I
4C86 -1-1 +-I - - ~ - - - - - - ,
I
L _ - _ _J I
I-output=
f·in
Divlde-by•N
Continued on next page.

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