8
STAR*TECH JOURNAL/DECEMBER 1982
The low output of OP-AMP RS is inverted by
F7 Pin 4. This high output is fed to the main
clock counter E4 Pin 14, which when high, will
clear or set to zero all outputs of E4. Holding
those outputs to zero prevents all major clocks
from pulsing, and without a clock, the MPU
cannot work.
The output ofF7 Pin 4 is also tied to F7 Pin
5, which inverts the high to a low on Pin 6. This
low presets flip-flop K3, which forces Pin 5
high and Pin 6 low. Pin 6 is the Reset line of the
MPU. The bar over reset means it is an active
low signal. This tells us the MPU will be in a
reset mode when Reset is low.
When the output of OP-AMP RS goes
high, counters E4 and H4 begin to clock. The
output of counter H4 Pin 6 then pulses once
which brings the Reset line high. From this
moment on, the MPU is operating.
In order for the MPU to execute the
program, the Reset line must be held high.
Should the Reset line go low at any point, the
MPU would reset and go back to its first
instruction in ROM. To prevent this from
happening, the Watchdog Clear (WDCLR)
signal clears or resets counter H4 to zero. This
prevents H4 Pin 6 from pulsing high, which
prevents the Reseiline from pulsing. Therefore,
WDCLR is a repetitive signal output from the
MPU at a precise moment, timed to always
clear H4 before it has a chance to count
through to Pin 6.
Should the MPU receive invalid data, it
would become "confused" and forget to address
the WDCL: signal at the proper time, thus
causing the eset line to start pulsing. Some of
the main items that might cause this are listed
below:
I.Bad ROM
2.Bad RAM
3.Bad MPU
4. Shorted Address and Data Lines
5. Bad Address and Data Buffers
6. Open Traces
7. Bad Switch input buffer or multiplexer
Figure 2
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