Star Tech Journal

Issue: 1982-December - Vol 4 Issue 10

STAR*TECH JOURNAL/DECEMBEtMNUFACTs
O
7
ATARI POWER-ON RESET AND WATCHDOG CIRCUITS
By Frank Becker, Atari, Inc., Somerset, NJ
The purpose of the Power-On Reset Circuit is
to hold the reset line to the MPU low until the
power supply five volts stabilizes. This will
insure that only valid information is present on
the address and data lines when the MPU is
initialized.
The OP-AMP RS is configured as a differ-
ential input or difference amplifier; this means
it amplifies the difference between both input
pins. In analyzing this particular circuit, we see
a voltage divider network consisting of resistors
R69 (22K) and R72 (lOK) tied to 10.3 volts.
This produces approximately 7 volts on Pin 3,
the non-inverting input, when the 10.3 volts
reaches its maximum value. The inverting
input, Pin 2, has 5 volts applied to it.
Looking at Figure 1, we have 7 volts on the
positive input and 5 volts on the negative input.
We then perform more simple math to find out
if the differenc between the inputs is positive or
negative. 7 - 5 = 2. Because the difference
between the inputs is positive, the OP-AMP's
output will try to go as high as it can; however,
it will be limited to the OP-AMP's positive
power supply which is 10.3 volts. If the difference
had been negative, the output would have gone
as far negative as possible, in this case only
down to ground.
To summarize the operation of the OP-
AMP in this configuration, it can be stated that:
If the difference between the inputs is
positive, the output will be + Vee.
If the difference between the inputs is
negative, the output will be - Vee.
Refer to Figure 2 on page 8. You might now
expect to find the output of RS Pin 1 at 10.3
volts, and you would if it wasn't for the 220-
ohm resistor R73; R73 keeps the output at
about 5 volts. Diode CR3 protects the input to
F7 by clamping the input at 5 volts, should the
OP-AMP's output rise above 5 volts.
The output, Pin 1, will then be 5 volts
except during power-up. During power-up the
output will stay low for a very short time to
allow the five volts to stabilize. This occurs
because the resistor values of the voltage
divider are chosen to insure that Pin 3 never
goes higher than Pin 2 until the 5 volts stabilizes.
(Continued on next page.)
10k
Figure 1
68k
220A.
R72
22k
m
m
10.3
7v
R69
Vout
5.0v, >-----2---1
TO HAVE
T.
MODEL 125 • ARCADE JOYSTICK
The only sensible replacement
• manufac;tured from aluminum stru
• all mechanical fasteners of aircraft ty
• contact plates made of STAINLESS S
• gold contact points
• 2,4, or 8 positions
This unit ~ designed to give you and your
joy possible.
NEWPORT CONTROLS
7330 ADAMS STREET
PARAMOUNT, CA 90723
(213) 633-4494
®
8
STAR*TECH JOURNAL/DECEMBER 1982
The low output of OP-AMP RS is inverted by
F7 Pin 4. This high output is fed to the main
clock counter E4 Pin 14, which when high, will
clear or set to zero all outputs of E4. Holding
those outputs to zero prevents all major clocks
from pulsing, and without a clock, the MPU
cannot work.
The output ofF7 Pin 4 is also tied to F7 Pin
5, which inverts the high to a low on Pin 6. This
low presets flip-flop K3, which forces Pin 5
high and Pin 6 low. Pin 6 is the Reset line of the
MPU. The bar over reset means it is an active
low signal. This tells us the MPU will be in a
reset mode when Reset is low.
When the output of OP-AMP RS goes
high, counters E4 and H4 begin to clock. The
output of counter H4 Pin 6 then pulses once
which brings the Reset line high. From this
moment on, the MPU is operating.
In order for the MPU to execute the
program, the Reset line must be held high.
Should the Reset line go low at any point, the
MPU would reset and go back to its first
instruction in ROM. To prevent this from
happening, the Watchdog Clear (WDCLR)
signal clears or resets counter H4 to zero. This
prevents H4 Pin 6 from pulsing high, which
prevents the Reseiline from pulsing. Therefore,
WDCLR is a repetitive signal output from the
MPU at a precise moment, timed to always
clear H4 before it has a chance to count
through to Pin 6.
Should the MPU receive invalid data, it
would become "confused" and forget to address
the WDCL: signal at the proper time, thus
causing the eset line to start pulsing. Some of
the main items that might cause this are listed
below:
I.Bad ROM
2.Bad RAM
3.Bad MPU
4. Shorted Address and Data Lines
5. Bad Address and Data Buffers
6. Open Traces
7. Bad Switch input buffer or multiplexer
Figure 2
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ESET

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