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To determine which failure mode we have:
S* T JUNE 1981 7
1 - Connect Signature Analyzer ground-board ground.
2 - Connect Logic Pulser power leads to board (+5 & Ground)
3 - Put Signature Analyzer Probe to inverter output
4 - Place Logic Pulser tip to inverter output.
5 - Activate pulser, either 1 shot or 5 HZ mode.
6 - If the Signature Analyzer Probe pulse light pulses the fault is at point A or C. To isolate the fault further, lift or clip the pin at the output of the
inverter and if the output gives the proper signature, UPFF, then the input of the second inverter is bad, if you still have 0000 then the first inverter
is bad.
7 - If in 6 above the pulse light does not pulse then you have a physical short
FIGURE 2 •
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UPFF
A
FIGURE 3
FIGURE 4
B
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FIGURE 5
FIGURE 6
C
p
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u
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q3
Figure 6 shows address lines from a CPU to buffers (G3) to the address bus.
Proper signatures at the CPU and input of buffers but incorrect at buffer output
is a fault mode. Where you find 2 or more incorrect but some signatures this
indicates two bus lines shorted together.
Figure 7 shows a counter which has an incorrect signature (47C3) on pin 13
but correct signature on the other pins. To determine if the IC is bad, lift or clip
pin 13 and take the signature from the pin. If it is correct you will find another
signature on the trace showing a short trace. Incorrect signatures on the lifted
or slipped pin indicates a bad IC.
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FIGURE 7
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FIGURE 8
C
p
u
Ac;
ul
Figure 4 shows a gate or line with a failure mode "stuck at 1 ". This is fault
isolated the same for a "stuck at O".
Figure 5 shows the signatures (or probes) indications for a broken trace.
Note: In any test we must check to be sure the device has proper voltages.
For the CPU we must also be certain we have clock both %1 & ¢2, if
required. A properly designed NOP will eliminate the possibility of an
interrupt causing a CPU lockup.
Once we have determined we have an operational CPU with proper signatures
on each address pin, each address line can be traced to its termination. Figure
8 shows the logical test progression for the address bus. Checking inputs of
the bus drivers and then the outputs assure you that the address bus is clear.
If it isn't, use the fault isolation instructions given you.
All devices are now being properly addressed so we are ready to begin to
measure their response.
NEXT MONTH: Address Decoders, Roms, Rams, Sync and Timing Chains.