Classic Mode

Star Tech Journal

Issue: 1981-June - Vol 3 Issue 4

S*TJ
JUNE 1981
6
ANALYSIS (Part 2)
by Jim Snead, General Manager, Electronics Division,
Kurz-Kasch, Inc., Dayton, Ohio
To test a CPU we must give it an instruction which it can execute in a repetitive fashion and generate signatures which are stable and the same for all
like CPU's (8080's, Z-80's, 6502's, etc.). This instruction is "NOP''. (See figure 1 ). In order that we can be assured the CPU will only see this
instruction we must break the data bus and "hardwire" the NOP into the CPU. This is done by a NOP fixture.
(This NOP fixture does a few other things such as disable the interrupts so the processor will run.)
FIGURE 1 - CPU NOP FIXTURE CONNECTIONS
1
A .,
2
A,,
A,,
~ A,>
RESET
TSC
NC
~ A .'
i2
~ ;-•
1
D,
RESET
DBE
NC
6
D,
R/W
R/W
D,
8
o,
o,
9
D,
10
D,
D,
D, r - = - - t
D,
D,
D,
Ml
RESET
BUSRO
BUSAR
A,
A,
A,,
A,.
A,,
A,,
A,,
A,
·A,
D,
D,
31
JO
D,
29
D,
D,
D,
A,,
28
21
26
A,
A,
-SV
RESET
A,
'
+12V
A,
A,
A,
A,.
WAIT
WR
SYNC
+SV
A,,
Z 80
A,,
i2
DBE
NC
D,
WAIT r - + - - ~
A,,
GND
TSC
NC
6502
6800
READY
8080
0 -THESE PINS CONNECT DIRECT FROM LOGIC BOARD CPU SOCKET TO FIXTURE SOCKET PINS
WITHOUT 0- ARE INTERCONNECTED AS SHOWN. THESE PINS ARE NOT CONNECTED TO LOGIC BOARD CPU SOCKET.
FIGURE 1A - NOP FIXTURE SIGNATURES - FOR PROCESSORS
PROCESSOR
Z-80
8080
6502
CLOCK
PIN 21
PIN 17
PIN 37
START/STOP
5
36
25
GROUND
29
2
21
AO
30
25
uuuu
9
uuuu
A1
FFFF
31
5555
26
10
A2
32
cccc
27
11
8484
A3
33
7F7F
29
12
P763
A4
34
5H21
30
13
1U5P
AS
OAFA
35
31
14
0356
A6
36
UPFH
32
15
U759
A?
37
52F8
33
16
6F9A
A8
38
HC89
34
17
7791
A9
2H70
39
35
18
6321
A10
HPPO
40
1
19
37C5
A11
1
1293
40
20
6U28
A12
HAP?
37
4FCA
2
22
A13
3C96
38
23
4868
3
A14
24
9UP1
4
3827
39
A15
5
755P
36
25
0002
vcc
0001
0003
6800
PIN 37
25
21
9
10
11
12
13
14
15
16
17
18
19
20
22
23
24
25
The NOP instruction causes the CPU to become a
65K counter with its 16 address lines being the
outputs. If the address outputs are counted through
from all "O's" to all "1 's", then the address bus has
been exercised for all possible combinations and it
does this repeatedly. Each of the address lines Ao -
A15 have a unique signature unless there is a fault
with the processor or a trace or a device connected to
that address line. (Figure 1 A).
To obtain the signature for the address lines we
use the system clock and as in all counters (remem-
ber the CPU is now a counter) the start and stop go to
the most significant bit. Since we wish to input the
maximum number of clock pulses we start and stop
on the A 15 leading edge. (See 5* TJ Vol. 3, No. 3.)
SOME COMMON FAULT SIGNATURES
I HOW TO DEAL WITH THEM
Figure 2 shows a normal inverter chain with signatures
you might expect
Figure 3 we see a proper signature on the first
inverter's input and a "stuck at O" at the output. As
shown at points A, B & C we can have 3 failure modes.
Point A is a failed output on the inverter, Point B
would be a physical short to ground and C, a failed
inverter input
J
To determine which failure mode we have:
S* T JUNE 1981 7
1 - Connect Signature Analyzer ground-board ground.
2 - Connect Logic Pulser power leads to board (+5 & Ground)
3 - Put Signature Analyzer Probe to inverter output
4 - Place Logic Pulser tip to inverter output.
5 - Activate pulser, either 1 shot or 5 HZ mode.
6 - If the Signature Analyzer Probe pulse light pulses the fault is at point A or C. To isolate the fault further, lift or clip the pin at the output of the
inverter and if the output gives the proper signature, UPFF, then the input of the second inverter is bad, if you still have 0000 then the first inverter
is bad.
7 - If in 6 above the pulse light does not pulse then you have a physical short
FIGURE 2 •
{>o
U ? F \:\
UPFF
A
FIGURE 3
FIGURE 4
B
J
troooo
_U---'--P_F_H_[:t vc~
V CC.
J
B
~oooo
FIGURE 5
FIGURE 6
C
p
7
u
S5
l~S S
q3
Figure 6 shows address lines from a CPU to buffers (G3) to the address bus.
Proper signatures at the CPU and input of buffers but incorrect at buffer output
is a fault mode. Where you find 2 or more incorrect but some signatures this
indicates two bus lines shorted together.
Figure 7 shows a counter which has an incorrect signature (47C3) on pin 13
but correct signature on the other pins. To determine if the IC is bad, lift or clip
pin 13 and take the signature from the pin. If it is correct you will find another
signature on the trace showing a short trace. Incorrect signatures on the lifted
or slipped pin indicates a bad IC.
~
FIGURE 7
Cl oc I<.
-6
5
'I
3
2 71fl f. I
II '?-- ,;
O }02..
l'f
~
-:I:.
c..
::)
:::)
t')
\I)
0
? \J
r-
~
FIGURE 8
C
p
u
Ac;
ul
Figure 4 shows a gate or line with a failure mode "stuck at 1 ". This is fault
isolated the same for a "stuck at O".
Figure 5 shows the signatures (or probes) indications for a broken trace.
Note: In any test we must check to be sure the device has proper voltages.
For the CPU we must also be certain we have clock both %1 & ¢2, if
required. A properly designed NOP will eliminate the possibility of an
interrupt causing a CPU lockup.
Once we have determined we have an operational CPU with proper signatures
on each address pin, each address line can be traced to its termination. Figure
8 shows the logical test progression for the address bus. Checking inputs of
the bus drivers and then the outputs assure you that the address bus is clear.
If it isn't, use the fault isolation instructions given you.
All devices are now being properly addressed so we are ready to begin to
measure their response.
NEXT MONTH: Address Decoders, Roms, Rams, Sync and Timing Chains.

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