Play Meter

Issue: 1981 May 01 - Vol 7 Num 8

LESSON 6:
Diode Gate Design
A
8
X
A
II
X
0
0
0
0
I
0
I
0
I
I
I
I
I
I
0
0
0
I
0
0
0
I
I
I
OR Colt
AND Co le
1·1 ~
F i g,
Truth tebltt tor AND and OR t a les . A 0
r t pt t . . nll
a low voltage level and a I a hlth voltat• level .
-V
Oucput
R
Th is lesson will introduce the
student to logic and truth tables
as well as the design of diode
gates. Both AND and OR gates
are covered .
Logic Gates and Truth Tables:
Logic gates are circuits which
have a single output and two or
more inputs the state of the out-
put is a funct ion of a set of rules
concerning the states of the in-
puts. For example, the output of an
AND gate is a high level if and only if
all of the inputs are at a high level.
The output state of an OR gate is a
high level if one or more of the inputs
is at a high level.
F ig . 1 ·2 . A
IC:hemt~tlc
dlatretn of 1 two Input di ode OR ,. ,, ,
-\1
"
-V
8
x.
II• OJ
~
A
~
" .,. 9 .,.
..,.
..,.
Fig . l · l . A d iagram ot a diode OR gate with all of the poas lbla
Input stat ...
-V
-V
R
F it . 1--4. A .c.hem1tlc dlattam ot • two Input diode AN D gate.
The studen t shoul d compare th i s circu i t to thet ot the OR ,.,,
In F i t . 1-2.
-V
-V
-V
-V
-V
-V
A«D
"
R
0
H
-v·
1
Fit. W . A di . . MI of • diode AND t•t• with all of tM
po.,llllt Input atatat .
PLAY METER, May 1, 1981
Instead of defining a logical
operation in words, an alternative
method is to define a high level as
logic 1 and a low level as logic 0.
Also , a truth table can be drawn . It
will contain all possible input
states and their corresponding
output state. In fig. 6-1 are the
truth tables for two input AND
and OR gates. The inputs are
labled A and B and the outputs
is labled X. Notice that the
defin itions given above are con -
sistent with the truth tables.
Diode OR Gates:
The circuit in fig. 6-2 is a diode
OR gate. The circuit operates as
follows : When both the A and B
inputs are at a logic 0, both diodes
are zero-biased , and no current
flows through the resistor R.
When no current flows , the
voltage drop across R is, of
course, zero. Therefore, the out-
put X is a a logic 0. This condition
isillustrated in fig . 6-3, section 1.
When either output A or B is
at logic 1, a current will flow
through R. When a current flows
through R the output raises to a
voltage V' because of the voltage
dropped across R. Therefore, the
output X is a log ic 1. It is easily
seen in fig. 6-3, section 2, that V' is
VF less than V. Also, notice that
the current through the diode is 1
plus the leakage current (IR) of
the zero-biased diode.
The condition of both A and B
inputs at logic 1 is illustrated in
section 3 of fig . 6-3. Notice that I is
now divided between both diodes
and that output X is at a logic 1.
The student should veri fy that the
operation of the diode OR gate in fig.
6-2 is consistent with the OR gate
truth table in fig. 6-1 . Fig. 6-3 should
be used as an aid for translating the
circuit to the truth table.
Design Procedure:
I V ' I·
STEP 1 : De termin e
VF is generally stated on the manu-
facturers ' data sheets. However, as a
general rule: VF for silicon diodes H
0.6V, and for germanium diodes, 02V
can be used.
STEP 2: F ind I.
I v 'I
I
R
Design Example:
Design a two-input diode OR
gate where R is a 6V, 150-omega
lamp. Use a silicone diode type
1N914. (The circuit diagram is
shown in fig. 6-2.
STEP 1 : Determ ine
6.0V - 0 .6V
=
The
IV ' I .
=
5 .4V
general rule for si licon
diodes is used.
STEP 2: Find I.
I
=
V,
R
5.4V
1500
38m a
Diode OR Gates:
The circuit in fig. 6-4 is a diode
AND gate. The circuit operates as
15
continued from previous page
follows: When inputs A and Bare
at a logic 0, both diodes are
forward-biased . When the diodes
are forward-biased, V' equals VF
of the diodes. therefor, X is at a
logic 0 . Section 1 of fig. 6-5 illus-
trates this condition . When input
A orB i at a logic 1, the state of in-
put X is at a logic 0 as shown in
section two of the figure .
However, when both inputs A and
Bare at a logic 1, both the diodes
PROGRAMMED TEST/6
are zero-biased and V' then
equals V. The output X is then at
logic 1 as shown in section 3.
Calculations for the AND gate are
the same as for the OR gate of the
previous paragraph.
1
A circuit wh ich generates a high level at
the output only when all of the inputs are
at a high level is called an:
a. AND gate
GO TO BLOCK 10
b.
OR gate
GO TO BLOCK 20
2
YOU ARE INCORRECT!
B
X
The student should verify that the
operat ion of the d iode AND gate in
fig . 6-4 is cons istent with the AND
gate truth table in fig . 6-1 . Fig . 6-5
should be used as an aid for
translating the circuit to the truth
table .
Use this truth table to work problem.
What is I ?
go on but check.
a:
As in previous lessons · programmed tests,
start at block 1 and follow the numbered
instruction associated with your answer.
A
I= -----------:--
GO TO BLOCK 13
End of Lesson Six
You have completed the test for Lesson
Six .
10YOU ARE CORRECT!
20
A circuit which generates a high level at
the output when any or all of the inputs are
at a high level is called an
Refer to the text and return to BLOCK 1.
a.
AND gate
OR gate
GO TO BLOCK 2
GO TO BLOCK 21
YOU ARE INCORRECT!
21 YOU ARE CORRECT!
11 YOU ARE INCORRECT!
When using a truth table, a high level at the
in put or output is called a
a. Logic 0
GO TO BLOCK 11
b.
Logic 1
GO TO BLOCK 3
Refer to the text and return to BLOCK 21 .
22 YOU ARE INCORRECT!
b.
Refer to the text and return to BLOCK 10.
Refer to the text and return to BLOCK 3.
12 YOU ARE CORRECT!
3
YOU ARE CORRECT!
Again referring to a truth table a low level
at the input or output is called a
a. Logic 0
GO TO BLOCK 12
b.
Logic 1
GO TO BLOCK 22
What is V' or the output voltage when X = a
logic 1 ?
4
a:
Design a two-input diode OR gate where
R = 10K and V = 10V. Use silicon diodes.
V' = 10V -0.6V = 9.4 V
V' =
-----G~O-::--:T-:0-
B-
L 0--:-
C-:
K-:2-3
V'= V -10x VF = 10-6 = 4V
Because the input to the second gate is
the output of the first gate and so on, the
output of the chain will decrease as pro-
protionate to the length of the chain. Th is
fact puts a serious limitation on the use of
the diode gates.
23
13
1 = 9.4V = 0. 94ma
10K
The general rule for silicon diodes was
used.
Did you get the same result. If not, do not
go on but check .
If there were a chain of ten didoes OR in
series, what would V' be for th e final
stage?
a: V' =
GO TO BL OCK 4
[END OF PROGRAMMED TES T/6]
Did you get the same result? If not, do not
BREADBOARD FOR LESSON 6:
Diode Logic Gate Design
1.
"Wire up" the circuit in figure
1 on the breadboard. Before
applying power, set switches S1
and S2 in the low (L) position.
of the Truth Table . It reads input A
is at a logic 0 and input B is at a
logic 0 and the output X is at a
logic 0.
2. Apply power, -6V only . The
lamp should be lit.
When both inputs are at a logic 0,
diodes 01 and D2 are both
forward biased , and the output is
a logic 0 . This operating
condition is illustrated in section
1 of figure 6-5.
The logic is shown in the top row
3.
16
Set S1 to the high (H)
position . The Imp should remain
I it.
When S1 is in the high position
providing a logic 1 at input A,
diode 01 is zero biased . However,
D2 is still forward biased ,
clamping the output to a logic 0 .
This operating condition is
illustrated in section 2 of fig ure
6- 5.
The student should state this
logic cond ition in the second row
of the Truth Table.
4.
Set S1 to the low (L) position
and S2 to the high position . The
lamp should remain lit.
This operating condition is identi-
cal to the previous cond ition in
paragraph 3. The exception being
the states of D1 and 02 are
reversed . The student should
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